package uart2 

import chisel3._
import chisel3.util._

class Uart_TX_IO extends Bundle{
    val clk             =   Input(Clock())
    val rst_n           =   Input(Reset())
    val tx_data         =   Input(UInt(8.W))
    val tx_data_valid   =   Input(Bool())
    val tx_data_ready   =   Output(Bool())
    val tx_pin          =   Output(Bool())
}

class Uart_RX_IO extends Bundle{
    val clk             =   Input(Clock())
    val rst_n           =   Input(Reset())
    val rx_data_ready   =   Input(Bool())
    val rx_pin          =   Input(Bool())
    val rx_data         =   Output(UInt(8.W))
    val rx_data_valid   =   Output(Bool())
}


class uart_tx extends BlackBox(Map(
    "CLK_FRE"   ->  100 ,
    "BAUD_RATE" ->  115200
)) with HasBlackBoxResource{
    val io = IO(new Uart_TX_IO)
    addResource("/uart_tx.v")
}

class uart_rx extends BlackBox(Map(
    "CLK_FRE"   ->  100 ,
    "BAUD_RATE" ->  115200
)) with HasBlackBoxResource{
    val io = IO(new Uart_RX_IO)
    addResource("/uart_rx.v")
}